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rev 0.6 / dec. 2009 1 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 32gb nand flash H27UBG8T2A http://
rev 0.6 / dec. 2009 2 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash document titl e 32gbit (4096 m x 8 bi t) nand flash memory revision history revision no. history draft date remark 0.0 i n i t ia l d r a f t . ma y . 22. 200 9 p r e limina ry 0.1 update pkg outli n e. add marking information . ju n. 17 . 200 9 p r e limina ry 0.2 update pkg i n f o rma t ion. update multi plane cache pr ogr a m. ju l. 16. 200 9 p r e limina ry 0.3 corre ct mul t i plane cache pr ogr a m op er a t io n timings (figur e 22) correct ra ndom d a ta in pu t ti mings (fi g ure 2 4 ) update pkg mecha n ical da ta (fig ur e 2-1) corre ct restricti o n read status i n multi plane operation (figure 63) a u g . 3 1 . 2 009 p r elimina r y 0.4 correct7 . 5 r e s t ri ction of r e ad s t atu s v a lu e i n m u l t i pl an e op er ati on corre ct7 . 6 . p a ge pr ogr a m f a i l ur e sep . 21 . 20 09 p r elimina r y 0.5 correct4.3 mult i pl an e p a g e r e ad oct. 5. 2009 p r elimina r y 0.6 cha n ge 52- vlga con t act, x8 de vice (figu r e 2) update pkg mecha n ical da ta (fig ur e 2-1) update pin d e scription of ce# cha n ge endur a nce change ac timing char acteristics (trc, t r p , twc, twp , tcls , tcs , ta ls , tds , trea, tadl) update r e ad id table (3r d byte) cha n ge bad block ma na gement d e c. 14 . 2 009 p r elimina r y
rev 0.6 / dec. 2009 3 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash product feature mult ilev e l cell t e chnol o gy sup p l y vo lt age or ganization page read time ? ? write time ? ? operat ing current h a rd wa re da ta pr ot ect i on en dur a n c e data retention - 10 y e ars pac k ag e - t sop (1 2x20) unique id f o r copyright protection
rev 0.6 / dec. 2009 4 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 1. su mmary de scription the produ c t pa rt no.(h2 7ubg8 t 2a) is a sing le 3.3v 3 2 gbit na n d flash me mory . t h e dev i ce conta i n s 2 p l a n es in a single d i e. each p l a n e is made u p of the 10 24 block s. ea ch block con sis ts of 256 program m able pa ges. each pa ge con t ains 8 , 64 0 b y tes. the pa ges a r e su bdivided in to a n 8 192-byte s main data stora g e a r ea with a spa r e 448 -by t e district. page program oper ation can be perf ormed in ty pical 1,600u s, an d a sing le block can b e era sed in ty pical 2.5ms. on-chip control logic unit aut o ma tes era s e a n d p r ogra m opera t ions to m a xim i ze cycle e n durance . e/w endura nce is s t ipulated a t 3 , 00 0 cycles wh en u s ing re le van t ecc an d error man a ge ment. the h2 7ubg 8t2a is a be st solu tion for app l icat io ns re quiring larg e no nv olatile storag e memory . 1.1. product list table 1 pa rt number organization vcc range pa ck age h27ubg8t2 a x8 2. 7v ~ 3.6v 48 - tsop1 52 - lga
rev 0.6 / dec. 2009 5 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash nc nc nc nc nc nc r/b re ce nc nc vcc vss nc nc cle ale we wp nc nc nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 12 13 37 36 25 48 1 24 nand flash tsop1 (x8) ' $ ',( $ h % / . ( ( & &3 $ 1 . 2. packaging info rmati o n gg 0 figure 1. 4 8 -t sop1 contact, x8 device 48-tsop1 - 48 - l ead plastic thin small o u t line, 12 x 20mm, package mec h anic al data symbol millimeters min typ max a 1.20 0 a1 0.050 0.15 0 a2 0.980 1.03 0 b 0 .170 0.25 0 c 0 .100 0.20 0 cp 0.10 0 d 1 1.9 10 1 2.0 00 12.120 e 1 9.9 00 2 0.0 00 20.100 e1 1 8 .3 00 1 8 .4 00 18.500 e 0 .500 l 0 .500 0.68 0 alpha 0 5 0 figure 1-1. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline
rev 0.6 / dec. 2009 6 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash nc nc nc nc nc nc nc nc vcc nc /we /wp vss io0 io1 io2 io6 io7 io5 io4 vss io3 r/b nc nc nc nc nc nc vcc nc vss vss vcc vcc nc cle ale /ce /re nc nc nc nc nc nc nc vss nc a b c d e f g h j k l m n 12 3 4 5 6 7 08 oa ob oc od oe of nc nc nc figure 2. 52-vlga contact, x8 device
rev 0.6 / dec. 2009 7 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 52-vlga, 14 x 18mm, package mechanical data symbol millimeters min typ max a 1 7 . 9 0 18.00 18 .10 a 1 13.00 a 2 12.00 b 1 3 . 9 0 14.00 14 .10 b1 10.00 b2 6 . 00 c1 . 0 0 c1 1 . 5 0 c2 2 . 0 0 d1 . 0 0 d1 1 . 00 e 0 .80 0 . 9 0 1 .00 cp1 0 .65 0 . 7 0 0 .75 cp2 0 .95 1 . 0 0 1.05 % $ $ $ fs ( fs & & & % % '' 0 & $% 0 & $% figure 2-1. 52-vlga, 14 x 18mm, packag e outline (top view through package)
rev 0.6 / dec. 2009 8 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash vcc vss wp# cle ale re# we# ce# i/o0~i/o7 r/b# i/o7~i/o0 d ata i n put / outp uts cle c omm a nd latch ena b le ale a dd re ss la tch enable ce# c hip enabl e re# r ead enable r/b# r e ady / busy we# w ri te enable wp# w ri te pr otect vcc p owe r supply vs s g r o u n d nc n o connection pin diagr a m figure 3. pin diagram pin names
rev 0.6 / dec. 2009 9 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 1. 3. p i n des c ri pt i o n not e s: a 0.1uf capacitor should be connected betw een the vcc supply voltage pin and the vss gr ound pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operatio ns. pin name descrip t io n i/o0- i /o 7 da ta inpu ts/ou tpu ts the i/o pins a r e us ed to command l a t c h cycle, addres s input cycle, and da t a in-o ut cycles during read / wri t e ope r a t ions . the i/o pins float to high- z when the dev i ce is deselected or the outp uts a r e disabled. cle com m an d l a tc h en abl e thi s i n put acti v a tes the latching of the i/o i n puts i n side the com mand r e gister on the rising ed ge of w r ite enable (w e#) . ale ad dres s la tch en ab le thi s i n put acti v a tes the latchi ng of the i/o i n puts i n side th e addr es s r egister on the rising e dge of w r ite enab le (we#). ce# chip enab le thi s i n put contr o ls the selecti o n of the device. when the device is busy , ce# low doe s not de select the memory . the device g o es into stand-by mod e when ce# goes high during 10us in r e ad y state . the ce # sig n al is ignor e d when device is in busy state, a n d will not ente r sta n db y mode ev e n if the ce# goe s high. we# write enable thi s i n put acts as cl ock to latch comm and, addre ss and da ta. the i/o inputs are l a tched on the r i se edge of we#. re# read ena b le the re# input is the serial data-out contr o l , and when acti v e dri v es the data onto the i / o bu s. data is v a li d trea after the f a lling edg e of re# which a l so incre ments the inte rnal column addr es s counte r by one. wp# write pro t ect the wp# pin, when low , pr ovide s a ha rd w a r e p r otection ag ainst und esire d write oper a t ions. har d w a r e w r ite pr otection i s activ a ted when the w r i t e pr otect pin is low . i n t h is co ndi t ion m o dif y oper ation do not s t art and the content of the memory i s not alter e d. w r ite pr otect pi n is not latched by w r i t e e n ab l e t o e n s u re t h e p r ot ect i on e v en d u r i n g t h e p o we r up p h ase s . r/b# read y / bu sy th e r e ady / busy ou tput is a n ope n dr ain pin tha t signa l s the s t ate of th e mem o ry . vcc suppl y volt age the vcc supplies the power f o r all the op er a t ions. (r ead , w r ite, a n d er ase ) . vss groun d nc no co nn ected
rev 0.6 / dec. 2009 10 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash x decoder address register ale cle ce# we# re# wp# command interf ace logic progr am/er ase controller hv gener ation y decoder address register command register io buf f er & latch x d e c o d e r nand flash memory array 1 device = (8,192 + 448) bytes x 256pages x 2048 blocks = 36,238,786 kbits data register & sense amp column decoder vcc vss global data buf fer output driver a14-a32 a0-a13 i/o<7:0> 1.4. block diagram figure 4. block diagram
rev 0.6 / dec. 2009 11 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 1.5. array organization figure 5. array organization 1.6. addressing not e s: 1 . l mus t be se t to low. 2 . the device ignores any ad ditiona l a ddress input cy cle tha n req u ired. 3 . the address consists of column addre ss (a0~a13 ) , pag e add r ess (a14 ~ a21), pla n e addre ss (a22), and block addr ess (a23 ~ the las t addre ss). bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/ o7 1 st cy cle a0 a1 a2 a3 a 4 a5 a6 a7 2 nd cy cle a8 a9 a10 a 11 a1 2 a 13 l (1) l (1) 3 rd cycle a14 a 15 a16 a 17 a1 8 a 19 a20 a 21 4 th cycle a22 a 23 a24 a 25 a2 6 a 27 a28 a 29 5 th cycle a30 a31 a32 l (1) l (1) l (1) l (1) l (1)
rev 0.6 / dec. 2009 12 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 1.7. command set function 1 st cycle number of address cycles data input cycles 2 nd cycle number of address cycles data input cycles 3 rd cycle acceptable command during busy p a ge read 00h 5 - 30h - - - n o read for cop y -back 00h 5 - 35h - - - n o random da t a output 1) 05h 2 - e0h - - - no single/mul t i plane cache read 5) 31h - - - - - - no single/mul t i plane cache read end 5) 3fh - - - - - - n o read id 90h 1 - - - - - no read st a t u s reg i st er 70h - - - - - - y e s p a ge pgm (star t ) / cache pgm 5) (en d ) 80h 5 y es 10h - - - n o random da t a input 1) 85h 2 y es - - - - no cop y -back pgm 85h 5 o ption 10h - - - n o cache pg m (start) 5) 80h 5 y es 15h - - - n o bl ock era s e 60h 3 - d0h - - - no reset ffh - - - - - y es mu lti plane p age read 60h 3 - 60h 3 - 30h no mul t i plane cache read st ar t 5) 60h 3 - 60h 3 - 30 h/33h no mu lti plane read for cop y -back 60h 3 - 60h 3 - 35h no mu lti plane bl ock era s e 60h 3 - 60h 3 - d0h n o mu lti plane da t a out p ut 1) 3 ) 00h 5 - 05h 2 - e0h n o mu lti plane read st a t us register 78h 3 - - - - - y e s multi plane p a ge pgm / multi pl ane cache pgm ( e nd) 80h 5 y es 11 h ~ 8 1h 2) 5 y e s 10h no multi plane cop y -ba c k pgm 85h 5 o ption 11 h ~ 8 1h 2) 5 o ption 10h no mul ti plane cache pgm (start) 5) 80h 5 y es 11 h ~ 8 1h 2) 5 y e s 15h no
rev 0.6 / dec. 2009 13 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash not e s: 1. r a n d om da ta i n put/outpu t mus t be pe rf orme d in a selected pa ge. 2. an y comma nd be twe e n 1 1 h a n d 8 1 h is pr ohibited ex ce pt 70h , 7 8 h, an d ffh. 3. mu lti plan e r a ndom d a ta-ou t mu st be u s ed a f ter mult i plan e r e ad ope r ations (m ulti p l a n e p a ge r e ad , m u lti p l ane ca che r e a d an d mu lti plan e r e ad f o r cop y back ). 4 . d o not change p l a n e addr ess or de r when using al l mul t i pl ane o p er at ions. 5. all cach e oper ation (ca c he p r ogr a m, cache r e ad) is a v ailable only within a blo c k. 6. i n terlea ve ope r a t ion b e tween two chips ar e a llowed. mu lti pla n e r e a d sta t us (78 h ) can be us ed to check each chip s t a t us. it is p r ohibited to use r e ad s t atu s com m an d (7 0h) in inte rle a v e d oper ation . ca utio n: 1. an y u n def i n ed comma nd inp u ts a r e pr oh ibited ex cept f o r ab ov e comman d set. 2. mu lti plan e pa ge r e a d, m u lti plane cache r e ad, an d m u lti p l a n e r e a d f o r cop y - back must be us ed af ter m u lti p l a n e pr o gr amm e d pa ge, multi plane cach e pr ogr a m, and multi plane copy -ba c k pr ogr a m. 1. 8. m o d e s e l e c t i o n not e s: 1. x can be v i l o r v i h. h = lo gic le v e l high. l = lo gic le v e l l o w . 2. wp# sh ou ld be b i a s ed to cmos h i gh or cmos low f o r stan d-by mod e . 3. we# and re# durin g r e ad bu sy m u st be k eep on h i gh to pr ev ent unpla nne d com mand/a ddr ess / d a ta inp u t or to a v e rt uni n tende d data out. in this ti m e , on ly r e se t, r e ad s t atu s , a n d mu l t i pl an e r e ad sta t u s ca n be in p u tte d to the dev i ce . cle al e ce# we# re# wp# mode hl l h x re a d m o d e command input l h l h x a d d r e ss i n put ( 5 cy cles ) hl l h h wr i t e m o d e comma nd i n put l h 1) l h h a d d r e ss i n put ( 5 cy cles ) ll l h h d a t a i n p u t l l 1) l h x s eq uent ia l r e a d an d dat a ou t p ut xx x h 3) h 3) x d urin g r e a d ( b usy ) x x 1) xx x h d u r i n g p r o g r a m ( b u s y ) x x x x x h du ring er ase (bu s y) x x x x x l w r ite pr otect xx h x x ov/vcc 2) sta n d- b y
rev 0.6 / dec. 2009 14 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash start block no = 0 read ffh check column 8192 of the first page last block end entry bad block fail fail pass ye s block no. = block no. + 1 pass no read ffh check col. 8192 of the last page 1.9. bad block management d e vices with ba d block s ha ve th e sa me q u ality leve l and th e s a me a c an d dc ch ara c te ris t ics as de vices wh ere a l l the bl ock s a r e va li d. a bad bl ock do e s n o t a f f e ct the p e r f o r ma n c e o f valid blocks be caus e it is is olated from the bit l i ne and common source line by a se le ct tra n sistor. the dev i ce s a r e sup p li ed with all the locations i n si de va lid block s erase d (ffh). t h e b a d bl o c k i n fo r m a t io n is w r i t t e n pr io r to shipping. a n y block whe r e the 1s t byte in the spa r e a r ea of either the 1s t or the last pa ge does not conta i n ffh is a bad blo c k. th e bad bl ock information must be rea d bef o re any erase is attempte d a s the ba d block information m a y be erase d . for the system to be able to recogn ize the bad blocks bas e d on the orig inal info r m atio n it is recommended to c r eate a bad block ta ble following the f l owchar t sh own in fl ow chart 1. th e 1st block, which is placed on 00h block addr e ss, is gua r ante ed to be a va lid block a t the time of shipment. flow cha r t 1. bad block management flow cha r t notes: 1. do not try to e r ase the de tected bad blocks, because the ba d block info rmation will be lo st. 2. do not perf or m program and erase op eration in inv a li d block , it is impossible to guarantee the input data and to ens u re that th e fu nction is no rma l .
rev 0.6 / dec. 2009 15 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash block a block b data data failure ffh ffh buffer memory controller 1 page st 1 page st nth page nth page (2) (3) 1.10. bad block replacement this d e vice ma y ha v e the in v a lid blocks when ship ped f r om f a ct ory . an i n v a l i d bl ock is on e th at con t ai ns one or mo re bad bits. over the li f e time of the de vice addi tional b a d b l ocks ma y dev e lop . i n this cas e , the block has to be re pla c ed b y copy ing the data to a v a lid bloc k. these a dditional ba d blocks can be identi fied as at tempts to pr ogr a m or er as e them w i ll gi v e e r r o r s in t h e s t at u s r e gi st er . the f a ilure of a p a ge p r ogr a m oper ation does not af f e ct the d a ta in other pa ges in the sa me block. bad b l ock ca n be r e place d b y re -pr o gr amming the curre n t da ta and copy ing the re st of the r e placed b l oc k to an av ai la bl e v a l i d bl ock . r e f e r to t a b l e 2 and figur e 6 f o r the r e commended p r ocedur e to fol l ow i f an e r r o r occurs during an oper ation. table 2. block failure fig u re 6. blo c k replac ement notes: 1. a n error occurs on nth page of th e b l ock a du rin g program o r erase operati o n . 2. d a ta in block a is cop i ed to s a me locatio n in blo c k b which is vali d bl ock. 3. n t h pa ge of block a wh ich is in controller buf f er me mor y is copied into nth page of block b. 4. ba d block table s h ould be upda ted to prev ent f r om eras ing or programm ing block a. operation recommended procedure er ase b l o ck r e place m ent pr o g r a m b lo ck r e place m ent read ecc
rev 0.6 / dec. 2009 16 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2. electrical characteristics 2.1. valid blocks notes: 1 . the 1st block is gu ar ante ed to be a v a lid block at th e time of sh ipment. 2 . this sin gle device h a s a ma ximu m of 50 in v a lid blocks. 3 . i n v a lid blocks a r e on e th at contains on e or mor e bad bits. the d e vice ma y conta i n bad blocks upon shipment. 2.2. absolute maximum rating notes: 1. ex ce pt f o r the r a ting "o per a ti ng t e mper atur e r a nge " , s t r e sses a b ov e thos e liste d in the t a ble "a bsolute ma ximum r a tings" ma y ca use perma n ent dama ge to t h e d e v i ce . t h e s e a r e s t re ss r at i ng s on ly a n d o p er at i o n of the device a t thes e or an y othe r con ditions a bo v e th ose indicated in the oper ating se ctions of this specification is not implie d. exposu r e to ab solute maximum r a ting cond itio ns f o r extend ed periods ma y af f e ct device r eliabilit y . r e f e r also to the hy nix sure p r ogr a m a n d oth e r r e lev a nt qu alit y documen t s. 2 . minimum v o ltage ma y undershoot to -2v d u ring tr ansi tion and f o r less th an 20ns during tr a n sitions. symbol min typ max unit v a lid b lo c k number n vb 1998 2048 blocks symbol parameter value unit min t a ambient oper ating t e m p er atur e (commer c ial t e mper ature r a nge) 0 to 70 c ambient oper ating t e m p er atur e (extende d t e mper atur e r a nge) -25 to 85 c ambient oper ating t e m p er atur e (i ndustrial t e mper atur e r a nge) -40 to 85 c t bia s t e mper atur e un der bias -50 to 125 c t st g stor ag e t e mper atu r e - 65 to 150 c v io in put or ou tput v o ltage - 0.6 to 4 . 6 v v cc supp ly v o lta ge - 0.6 to 4 . 6 v
rev 0.6 / dec. 2009 17 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.3. dc and operating characteristics parameter symbol test conditions hy27ucg8t2a unit 3.3v min typ ma x power on reset current i cc0 f f h comma nd in put after power on -- 50p er device ? ope r ati n g curr ent re a d i cc1 t rc = t rc (mi n ), ce#=v il , i out =0 ? -- 5 0 ? pro g r a m i cc2 -- - 5 0 ? er ase i cc3 -- - 5 0 ? sta n d-by curr ent ( t tl) i cc4 ce#=v ih , wp#=0v/ v cc -- 1 ? stand-by curr ent (cmos) i cc5 ce #=vcc -0.2, wp#=0v/v cc -1 0 5 0 ? i n put lea k ag e curr ent i li v in =0 to v cc (m ax) -- 10 ? ou tput l e ak age cu rr ent i lo v out =0 to v cc(max) -- 10 ? i n put high v o ltage v ih - v ccx0.8 - vcc+0.3 v in p ut l o w v o l t a g e v il - - 0.3 - 0.2x vcc v ou t p ut h i g h v o lt a g e v oh i oh =-200 ? 2.4 - - v outp ut low v o ltage v ol i ol =2.1 ? -- 0 . 4 v output low curr ent (r/b#) i ol (r/ b #) v ol =0.4v 81 0 - ?
rev 0.6 / dec. 2009 18 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.4. ac test conditions not e s: 1 . these para meters are v e rified de vice cha r acteriz a tion an d are not 100% tes t e d . 2.5. pin capacitance (t a =25 c , f=1 . 0 ? ) 2.6. program/ read / e rase ch aracteristics not e s: 1 . typical v a lue is me asu r ed a t v cc =3.3v, t a =25 . not 100% te sted. parameter value 2. 7v vcc 3.6v input pulse lev e ls 0 v to v cc i n p u t r i se a n d f a ll ti mes 5 ? i n put a n d output tim i ng le v e ls vc c /2 output load (2.7v-3.6v) 1 ttl gate and cl=50 ? symbol parameter test condition min max unit c in i n put capa citance v in = 0v -1 0 ? c i/o input/output capacitance v in = 0v -10 ? parameter symbol min typ max unit p r ogr a m (fol lowi ng 10h) t prog - 16 0 0 50 00 ? cach e p r ogr a m (fol lowi ng 15h) t cbs y w - - 500 0 ? multi p l a n e pr ogr a m / multi p l a n e ca che pr ogr a m / multi pla n e cop y -back pr ogr a m (f ollowing 11h) t dbsy -3 5 ? c a ch e r e a d / m u l t i p l a n e c a ch e r e a d (f ollowing 31h/3fh ) t cb syr -3 2 0 0 ? b l ock er ase / mu lti pl an e b l ock er ase t be rs -2 . 5 1 0 ? n u mbe r o f par t ia l p r og r am c y c l es i n t h e same page nop - - 1 cy cl es
rev 0.6 / dec. 2009 19 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.7. ac timing characteristics parameter symbol 3.3v unit min ma x cle setup ti m e t cl s 12 ? cle hold time t cl h 5 ? ce# s e tup t i me t cs 20 ? ce# hol d t i me t ch 5 ? we# pulse width t wp 12 ? ale setup tim e t als 12 ? ale hold tim e t al h 5 ? data setup ti me t ds 12 ? data hol d ti me t dh 5 ? w r i t e cy cle time t wc 25 ? we # hi gh h o l d t i me t wh 10 ? data tr ansf er fr om cel l to r e gister t r 20 0 ? ale to re# de la y t ar 10 ? cle to re# de l a y t clr 10 ? re a d y t o r e # l o w t rr 25 ? re# pulse width t rp 12 ? we# high to busy t wb 10 0 ? re a d c y c l e t i m e t rc 25 ? re# access ti m e t re a 20 ? re# hi gh to output high z t rh z 10 0 ? ce# high to output hi gh z t chz 50 ? re# high to output hol d t rh o h 15 ? re# low to output hold t rl o h 5 ? re# o r ce# high to o u tp ut ho ld t coh 15 ? re# high hold time t re h 10 ? ce# low to re# low t cr 10 ? we# high to re# low t whr 80 ?
rev 0.6 / dec. 2009 20 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash notes: 1. if res e t com m an d (ffh ) is written at rea d y s t ate, the device g o es in to bu sy f o r maximum 5us. 2. program / er ase en able ope r ation : wp# h i g h to we# hig h . p r ogr a m / eras e disa ble opera t ion: wp # low to we# high . 3. the tran sition of th e corresp on din g contro l pins must occur only w h il e w e # is held lo w. 4. t adl is the time from th e we# risin g edg e of fin a l addre ss cycle t o the we# rising ed ge of f i rs t data cycle. re# hi gh to we # l o w t rhw 100 ? output hi g h z t o re# low t ir 0 ? a ddr ess to da ta loa d ing time t adl 100 ? de v i ce re se ttin g tim e (r ead / p r ogr a m / er ase ) t rst 20/30 /5 00 ? w r i t e p r o t ect i on t i m e t ww 100 ?
rev 0.6 / dec. 2009 21 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.8. status r e gister coding notes: 1. i / o0 : th is bi t is on ly v a lid f o r pro g ra m an d eras e op e r ati o n s . du rin g ca ch e p r og ra m o p e r a t ion s , this bit is only v a lid when i/o5 is set to one . 2. i/o1: this bi t is only va lid for cac h e program operations. th is bit is not vali d until after the second 15h comma nd or th e 10h comman d ha s bee n tra n sfe r red in a cach e progra m sequ ence . when cach e program is not sup porte d, th is bit is not us ed. 3 . i/o5: i f set t o one , then there is no array op eration in pr og ress. if clea re d to zero, then there is a com mand being proce ssed (i/o6 is clear ed to zer o ) or an array operat ion in pro g ress. when ov erlapp ed interlea ved ope r ation s or cach e com man ds are not su pported, this bit is not u s ed. 4 . i/o6: i f set to one , then the device or i n te rleaved address i s ready for another command and all other bits in the stat us value a r e valid . if cle a red to zero, t h en the las t comm and is sued is not ye t comp le te an d sta t us re gis t er bits<5:0> are invali d valu e. when cache ope r ations are in use , th en th is bit in dicates wh ethe r an oth e r comman d can be a ccepted, an d i/o5 indicates whethe r the las t op eration is complete. i/o pa ge program bl oc k erase read cache read cache program coding 70 h/ 78 h 0 p a ss/ f a il p a ss/ f a il n/a n/a p a ss/ f a il n pa ge p a s s : '0 ' f a il : '1' 1 n /a n/a n /a n/a p ass/ f a il n-1 pa ge p a s s : '0 ' f a il : '1' 2 n /a n/a n /a n/a n /a '0' 3 n /a n/a n /a n/a n /a '0' 4 n /a n/a n /a n/a n /a '0' 5 n /a n/a n /a r e ady / b u sy r e ady / b u sy re a d y / b u s y busy : '0' r e ady : '1' 6 r ea dy / bu sy r e ady / bu sy r e ady / busy r e a d y / bu sy r e ady / bu sy da ta ca ch e r e ad y / busy : '0 ' r e ad y : '1 ' 7 w ri te pr ote c t w ri te pr otect w rite protect w ri te pr otect w ri te pr otect protected : ' 0 ' not pr otected : ' 1 '
rev 0.6 / dec. 2009 22 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.9. device identifier coding 2.10. read id data table 2.10.1. 3 rd byte of device identifier description parameter symbol device i d entifier byte des c rip t ion 1 st ma nuf a c tur e r co de 2 nd de vice i d entifier 3 rd i n te rnal ch ip num ber , cell t y pe, nu mber of simultane o u s ly pr ogr a mme d p a ges , i n terlea v e d p r ogr a m , w r ite cache . 4 th p a ge s i z e , b l o c k si z e , r e du nda n t ar e a si z e 5 th plane number , ecc leve l 6 th technology (design rule), edo, interface part number voltage bu s width manufacture code dev i ce code 3 rd 4 th 5 th 6 th H27UBG8T2A 3.3v x8 adh d7h 94h 9ah 74h 42h 3 rd cycle description i/ o 7 i/ o 6 i/o 5 i/ o 4 i/ o 3 i/ o 2 i/ o 1 i/ o 0 internal chip number 1 2 4 re s e r v e d 0 0 1 1 0 1 0 1 ce l l t y pe 2 level cell 4 level cell 8 level cell 16 l e v e l c e ll 0 0 1 1 0 1 0 1 numb er of simulta n eous ly pro g r a mmed p a ges 1 2 4 8 0 0 1 1 0 1 0 1 in t e r l eave d p r og r a m bet w een mu lt i p le di c e supported not supported 0 1 wr i t e c a c h e not supported supported 0 1
rev 0.6 / dec. 2009 23 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2 . 10 .2 . 4 th byte o f devi ce ident i fi er descripti o n 2.10.3. 5 th byte of device identifier description 4 th cycle description i/o 7 i/ o 6 i/ o 5 i/ o 4 i/o 3 i/ o 2 i/o 1 i/ o 0 pa g e s i z e (without spare area) 2kb 4kb 8kb re s e r v e d 0 0 1 1 0 1 0 1 bl o c k si z e (wi t ho ut s p a r e a r ea) 128 kb 256 kb 512 kb 768 kb 1mb 2mb re s e r v e d re s e r v e d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 re d u n d a n t a r e a s i z e 128 b 224 b 448 b re s e r v e d re s e r v e d re s e r v e d re s e r v e d re s e r v e d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 5 th cycle description i/o 7 i/ o 6 i/ o 5 i/ o 4 i/o 3 i/ o 2 i/o 1 i/ o 0 pla n e nu mber 1 2 4 8 0 0 1 1 0 1 0 1 ecc lev e l 1b it/512byte s 2b it/512byte s 4b it/512byte s 8b it/512byte s 16 bit/512by tes 24 bit/204 8by t es 24 bit/102 4by t es re s e r v e d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 re s e r v e d 0 0 0
rev 0.6 / dec. 2009 24 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 2.10.4. 6 th byte of device identifier description 6 th cycle description i/ o 7 i/ o 6 i/ o 5 i/ o 4 i/ o 3 i/ o 2 i/ o 1 i/ o 0 nand technology 48n m 41n m 32n m re s e r v e d re s e r v e d re s e r v e d re s e r v e d re s e r v e d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 edo sup por t not support support 0 1 nand i n terf ace sd r dd r 0 1 re s e r v e d 0 0 0
rev 0.6 / dec. 2009 25 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash cl s cs wp command cle ce# we# ale i/ox dh ds als clh ch : dont care tt t t t t t t alh t 3. g timing diagram bus op er at ion there are six sta n da rd bus ope r a t io ns th at co ntro l the devi ce. these are comma nd input, address input, data input, data output, write protect, and st andby. 3.1. command lat c h cycl e ti mi ngs 0 f i g u re 7. comman d latch timings note: a l l c o m m a n d e x c e p t r e s e t , r e a d s t a t u s , a n d m u l t i p l a n e r e a d s t a t u s i s i s s u e d t o c o m m a n d r e g i s t e r o n t h e r i s i n g e d g e of we#, when cle is h i g h , ce# and ale is low, a n d de vice is not bu sy s t ate
rev 0.6 / dec. 2009 26 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash wc clh ch wp wh din 1 din final dh dh dh ds ds ds wp wp cle ale ce# i/ox we# als din 0 t t t t t t t t t t t t t t : dont care tcls tcs twc tals tals tals tals tals talh talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh tds col.add1 cle ce we ale i/ox col.add2 r ow add1 r ow add2 r ow add3 tds tds tds tds tdh tdh tdh tdh tdh : dont care 3.2. address latch cycle timings figure 8. ad dress latch timings 3 . 3 . input data latch cycle timings figure 9. inp u t data c y cle timing s not e : data input cycle is accepted to data register on the rising edge of we #, when cle and ce# and ale are low, and device is not busy state.
rev 0.6 / dec. 2009 27 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash rr chz rhz rhoh dout ce# re# i/ox r/b# rea dout rloh rea rp reh rc t t t t t t t t t t : dont care cr t reh rea rc rr chz rhz rhoh dout dout ce# re# i/ox r/b# dout rea rhz rea t t t t t t t t t t 3.4. data out p ut cycle timings (cle=l, we#=h, ale=l, w p #=h) 0 figure 10. data output cycle timings notes: 1. tra n sition is meas ured +/-200 mv f r om stea dy sta t e voltage with load . this pa ramete r is samp le d an d not 100 % te sted. ( t chz , t rhz ) 2. t rl oh is va lid when f r equ e ncy is highe r tha n 33 mhz. t rhoh s t a r ts to be v a lid when freq uen c y is lowe r than 33mhz. 3.5. data out p ut cycle timings (edo ty pe, cle=l, we#=h, a l e=l ) 0 figure 11. data output cycle timings (ed o ) notes: 1. tra n sition is meas ured +/-200 mv f r om stea dy sta t e voltage with load . this pa ramete r is samp le d an d not 100 % te sted. ( t chz , t rhz ) 2. t rl oh is va lid when f r equ e ncy is highe r tha n 33 mhz. t rhoh s t a r ts to be v a lid when freq uen c y is lowe r than 33mhz.
rev 0.6 / dec. 2009 28 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash t cls t clh t cs t wp t ch t cr t chz t coh t whr t alh t ar t rea t rhz t rhoh t ds t dh t alh t als wc t wp t wh t : dont care cle ce# we# ale re# i/ox 78h row.add1 row.add2 row.add3 status cle ce# re# i/ox we# 70h status output cls t clh t cs t clr t ch t cr t chz t rhz t rhoh t wp t whr t ds t dh t ir t rea t : dont care 3. 6. read s t a t us c y cle timings 0 figure 12. read status timings 3.7. multi plane re ad status timings 0 figure 13. multi plane read status timings
rev 0.6 / dec. 2009 29 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash ce# cle ale we# re# i/ox 00h col. add1 col. add2 row . add1 row . add2 row . add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t rhz dout m ce# cle ale we# re# i/ox 00h col. add1 col. add2 row . add1 row . add2 row . add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t clr t chz t coh t cs t ch t cls t clh 3.8. page re ad operation timings (r ead one p a ge) fi gure 14. p a ge read operat ion ti mings 3.9. page re ad operation timings (intercepted by ce#) figure 15. page read operation timings
rev 0.6 / dec. 2009 30 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3.10. page read operation timings with ce# don't care fi gure 16. p a ge read operat ion ti mings wit h ce # don't car e 3.11. random data output timings fi gure 17. random dat a output timings note: random data output is available within a page.
rev 0.6 / dec. 2009 31 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3 . 12 . mul t i pl ane page read operat io n with random data output timings figur e 1 8 . mult i pl ane page read oper at ion ti mings wit h random data output no tes : 1. multi p l ane pa ge ad dresse s are required to b e the same . 2. m u lti p l ane rand om data- o ut mu st be used afte r multi plane read ope r ation s . 3. multi p l ane page read must b e us ed af ter mult i pla n e p r og ramme d page , multi plane cache progra m, a n d multi plane copy-back program .
rev 0.6 / dec. 2009 32 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3. 13. ca che rea d op erati o n t i m i ng s figure 19. cache read operati o n ti mi ngs not e s: 1. th e colu mn a ddres s will be r e set to 0 by the 31h /3 fh comman d inpu t. 2. cach e read op eration is av ailable only within a block .
rev 0.6 / dec. 2009 33 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3.14. multi plane cache read ope ration timings figure 20. multi plane cach e read o p eration timings notes: 1. th e colu mn a ddress will be re set to 0 by the 31h/3fh com m an d inpu t. 2. cache read ope r ation is av aila ble only within a block . 3. ma ke su re to termina t e th e operation with 3f h com mand. i f the page read op eration is completed, issu e ffh re set be fore ne xt ope r ation . 4. mu lti pla n e p a ge addre sses a r e req u ired to be th e sa me. 5. mu lti pla n e ca che re ad mu st be used afte r multi plane progra mmed p a ge, mul t i plane cache program , a n d multi plane copy-ba c k program
rev 0.6 / dec. 2009 34 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash device code 3rd cy c. 4th cyc. 90h ce# cle we# ale re# i/ox 00h adh ar whr rea 5th cy c. 6th cy c. maker code t t t 3.15. read id op eration t i mings fig u re 21. read id op eration timings 3.16. page prog ram op eration t i mings fi gure 22. p a ge program operati o n ti mi ngs note: t adl is th e tim e f r om the we# r i sin g edge of fina l a ddr es s cycle to the w e # ri sing edge of first data cy cl e .
rev 0.6 / dec. 2009 35 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash k k k k k 'dwd 'dwd k 'dwd2xwsxw $gg&\fohv $gg&\fohv $gg&\fohv $a$9 dolg $a$)l[hg3/rz $0xvwehvdphzlwkwkhvrxufhsodqh $a$)l[hg3/rz $a$9 dolg $a$9 dolg $0xvwehvdphzlwkwkhvrxufhsodqh $a$9dolg &ro$gg 5rz$gg 6rxufh$gguhvv &ro$gg 5rz$gg &ro$gg 5rz$gg xswr %\wh'dwd xswr %\wh'dwd 'hvwlqdwlrq$gguhvv 'hvwlqdwlrq$gguhvv ,2[ 5% ,2[ 5% w'%6< w5 w352* 3.17. pag e program op eration timing s with ce# don't care fi gure 23. p a ge program operati o n ti mi ngs wit h ce # don't car e note: t adl i s the time f r om the we# rising edge of fi nal addre ss cy cl e to the we# rising e dge of fi rs t data cycle. 3.18. random data input timings fi gure 24. random dat a i n put timi ngs notes: 1 . t adl i s the time fr om the we# rising edge of fi nal addr ess cy cl e to t h e we# rising edge of first data cycle. 2 . r a nd om data input ca n be perf ormed in a pa ge.
rev 0.6 / dec. 2009 36 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3.19. multi plane page pr ogram ope ration timings figure 25. multi plane page pro g ram op era t ion timing notes: 1. any comm and between 11h an d 81h is prohibited except 70h, 78 h an d ffh 2. t adl is the tim e from th e we# risin g ed ge of f i n a l addr e ss cycle to the we# rising ed ge of f i rs t data cycle. 3. mu lti pla n e p a ge addre sses a r e req u ired to be th e sa me.
rev 0.6 / dec. 2009 37 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3.20. cop y -back program ope ration timings with random date input figure 26. co pyba ck program op era t io n ti ming wi th r a ndom data input no te: copy b a ck oper ation is allowed on ly with in the same memory p l a n e. 3.21. cache program o p eration timin g s figure 27. ca che p r og ra m operation timings no te: t prog = prog ram time for the las t page + program ti m e for the (la s t -1 )th page - (command input cycle time + address input cycle time + last page data loading time
rev 0.6 / dec. 2009 38 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3.22. multi plane cache pr ogram o p eration timing s figure 28. multi plane cach e program o p eration timings notes: 1. t pr og = program ti m e for the last page + program time fo r th e (last -1)th page - (co m man d i n pu t cycl e time + a ddres s input cycle time + last pa ge da ta loa d ing time) 2. ma ke su re to termina t e th e operation with 80 h-10h - comma nd se quence. if the op eration is term inated , is sue ffh reset b efore n ext op eration . 3. selected pa ge ad dress e x ce pt a22 with in two blocks m u st b e sam e .
rev 0.6 / dec. 2009 39 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3. 23. bloc k erase operat ion ti mi ngs f i g u re 29. bloc k erase operation timings 3.24. mult i plane eras e ope ration timings figure 30. multi plane erase operation timings
rev 0.6 / dec. 2009 40 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash ffh t rst ce# cle we# i/ox r/b# t wb 3. 25. rese t ti mi ngs figure 31. reset timings
rev 0.6 / dec. 2009 41 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash cle ale ce# i/ox we# r/b# re# 00h address (5 cycle) 30h data output (serial access) t r 4. device operation 4.1. page read this oper ation i s ini t ialized by 00h- 3 0h to the co mmand r e gi ster along with f o llowed b y five ad dr ess input cycles. the 8,640 by tes of da ta with in the selected p a ge a r e tr ansf e rre d to the data r e gi ste r s in less than 200 ? (t r ). the s y stem contr o l l er ma y dete ct the completion of thi s data t r ansf er 200 ? (t r ) by an alyz in g the ou tput of r/b# pin. once the da ta in a pag e is load ed into the data r e gisters , they ma y be r e a d ou t in 25 ? cy cle time by se quentia l ly pulsing re#. the r e peti tiv e high to l o w tr ansitions of the re# clock mak e the de vice output the data starting from the se l e c t e d col - umn a ddr ess up to the la st column a ddr ess. the d evice ma y outpu t r a nd om d a ta in a pa ge inste a d of th e consecutiv e s e que n tial data by writing r a ndom data out- put com m and. the colum n ad dr ess of next da ta , which is going to be out, ma y be cha n ged to the ad dr ess, which f o l- lows r a ndom da ta outpu t com m an d. r a n dom data ou tput ca n be ope r a t ed mu ltiple times, r e gar dless of how ma n y times it is done in a pa ge. figure 32. p a ge read random data output r a n d om data ou tpu t oper atio n ch an ges th e colu mn address fr om which d a ta is be ing r ead in the page re gister . r a n- dom da ta outpu t only is issu ed in r e a d y s t ate. r e f e r to figu r e 33.
rev 0.6 / dec. 2009 42 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash i/ox r/b# re# 00h data t r output address (5 cycle) 30h data output 05h address (2 cycle) e0h 30h 31h d0 ... dn 31h d0 ... dn 3fh d0 ... dn cle we# re# i/ox r/b# as defined for read t r t cbsyr column 0 t cbsyr column 0 t cbsyr column 0 f i g u re 33. rand om da ta output 4.2. cache read (available only wi thin a bl ock) to im prove p a ge read throughput, ca che read op eration is used w i t h i n a b l o c k . f i r s t s t e p i s s a m e a s n o r m a l p a g e r e a d , issuing a page read sequence (00 - 3 0 h). after rand om access (r/b# returns to hi gh), 31h command is l a tc hed into the com- ma nd register . da ta is be ing trans f erred f r om the data reg i ste r to the cache register. while ca che register data is outputted, next pa ge is trans f erre d f r om memory cell to data re gis t er. r/b# will stay lo w duri ng pres ent page ra ndom access ing and pre v ious pa ge transfe rring to cache regist er. because it is not necessary to output a whole pag e data bef o re is suing a n othe r 31 h co mma nd, if se ria l data o u tp ut time exceed s ra ndo m access time (t r ), th e ra ndo m ac cess ti me ca n be hi dden . t h e sub- se quent page s are issued ad ditiona l 31 h commands. to terminate cache read, 3f h co mma nd sh ou ld be issued. this com- mand transfer data from data register to the cache re gi s t er without issui n g next pa ge read. d u ri ng th e ca ch e rea d oper ation , de vice doesn' t allow an y other comma nd excep t cache re ad comman d (31h), read statu s (7 0h, 78h ), read (00h) , an d reset (ffh ). t o carry ou t ot her op erations af ter ca che operation, ca che read must be ende d by 3fh comm and or issue reset (ffh) be fore ne xt ope r ation. figure 34. cache read
rev 0.6 / dec. 2009 43 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address : v alid address (3 cycle) 60h 30h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid 00h address (5 cycle) address (2 cycle) 05h e0h data output 4.3. multi plane page read mu lt i p l a n e p a ge r e ad is an ex t e ns io n of pa ge r e a d , fo r a si ngle plane with 86 40by t e pa ge reg i ste r s. since the device is equ i p p ed with two m e mory plan es, activatin g the two sets of 8 640by t e pag e resisters ena ble s a ra ndom rea d of two page s. multi plane pa ge re ad is initiate d b y rep e ating comma nd 60h f o llowe d by th ree addre ss cycles t w ice. in this case , only sa me pa ge can be selected f r om each pla n e. afte r rea d con f irm comm and (30h ) the 17 280by t es of d a ta wi th in the selected two pa ges are tra n sf erred to th e d a ta registers in less than 200 ? (t r ). the system controller ca n detect the c o mpletion of data transfer (t r ) by monitori ng the ou tpu t o f r/ b# pin. once the data is l o aded i n to the data regi ste r s, the data output of fi rs t pl an e can b e read out by issuing com m and 0 0 h with fiv e addres s c y cles, comma nd 05h with two column addr e ss an d f i nally e0h. th e data o u tp ut of seco nd plan e ca n be re ad out using the identica l com mand sequence s. the restri ction s for m u lti p l a n e p a ge read are shown in figu re 35 . multi plane pa ge rea d must be used in the b l ock which ha s been program m ed with multi plane pag e progra m. figure 35. multi p l a n e pa ge read 4.4. multi plane cache read (avai l able only wi thi n a bl ock) the device suppo r t s multi plane cach e read , which ena b les high rea d throughput by re ading two pa ges in para llel. figur e 36 shows the command s e que n ce for the m u lt i plane cach e r e ad op eration. both conf ir m comma nds, 3 0 h and 33h, are vali d for the first pag e read sequence .
rev 0.6 / dec. 2009 44 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address : v alid address (3 cycle) 60h 33h page address : page m plane address : fixed high block address : block k b t cbsyr i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid 00h address (5 cycle) address (2 cycle) 05h e0h data output 31h figure 36. multi p l ane cache read not e s: 1. p l a n e 0 an d plane 1 sh ou ld be se le cte d with in the sam e chip 2. on ly on e block sh ou ld be se le cted from th e ea ch p l a n e. 3. m u lti plan e cach e read is av ai l a bl e o n ly within a block per plane. 4. selected p a ge addre ss except for a22 within two blocks mu st be same . 5. the ope r ation ha s to be term in ated with "3 fh" comman d . 4.5. r e ad id the device co ntains a product i d entificati on m o de , in itia te d b y writing 90h to th e comma nd register, f o llowe d by a n ad- dres s in put of 00h . six re ad cycles se quen ti al ly output the manufacturer code (a d h ), a n d the device code and 3rd, 4th, 5th, 6th cycle id, resp ectively . the com m and register re mains in re ad id mo d e un til fu rther co mma nds a r e issu ed to it. figure 37 shows t h e opera t ion sequence, while 2.10 read id data tables exp l a i n the b y te m e aning.
rev 0.6 / dec. 2009 45 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash cle ale we# re# i/ox 78h row.add1 row.add3 row .add2 status 90h cle we# ale re# i/ox 00h adh d7h 74h 42h 9ah whr 94h t 70h status cle we# re# i/ox figure 37. re ad id 4. 6. re ad status re gis t e r the device contains a sta t us register which m a y be re ad to fi nd o u t w h eth e r read, program or erase operatio n is com- pleted, and whethe r the pr ogra m or erase ope r ation is comple te d succes s fully. afte r wr iting re ad status (70 h ) or multi plan e read s t atu s (78h) comman d to th e com man d register, a rea d cycle outputs the content of the status re gister to t h e i/ o pin s on ly if c e # an d r e # ar e l o w , w h i c hev e r oc c u r s la st . t h i s t w o li n e c o nt r o l al lo w s t h e sy st em t o po l l t h e p r o g r e s s o f e a c h d e v i c e i n m u l t i p l e m e m o r y c o n n e c t i o n s e v e n w h e n r / b # p i n s a r e c o m m o n - w i r e d . r e f e r t o 2 . 8 . s t a t u s register co dings for spe c i f i c status register defi niti ons and figure 38, figure 39 for read s t a t us. th e comma nd reg- is ter rema ins in r e ad status mode until further comma nds a r e issu ed to it. ther efore, if the status register is read during a random read cycle, the read comm and (00 h ) sh ou ld b e given bef o re starting read cycles. figu re 38. re ad status figur e 3 9 . mult i pl ane read st at us
rev 0.6 / dec. 2009 46 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 80h address 5 cycle data input status 70h 10h cle prog t i/o 0 = 0 program pass i/o 0 = 1 program fail ce# ale we# re# i/ox r/b# 4.7. page program the d evice is programme d as a p a ge unit. the numbe r of cons ecutive p a rtial page pr ogra mming opera t ion within the s a me page wi thout an interven ing e r ase opera t ion must not exceed 1 tim e s. the p r ogra m addr essing should b e done in s e que n tial order in a block . a p a ge program cycle cons is ts of a se ria l data loading period in which u p to 8 640by t es of da ta m a y be loaded into the da ta register , followed by a non- volatile pr ogra mming pe riod wher e the loa d ed da ta is p r o- g r amme d into the appropriate cell. the s e rial data -loading period begins by i n putting the serial data input command (80h) , fol l ow ed by the fi ve cycl e addr ess inputs and then serial data. the by tes othe r than those to be programmed do not ne ed to be loa d ed. the dev i ce supports random da ta inpu t in a page. the column a ddres s o f ne xt da ta , which will be e n tered , may be changed to the add r ess which follows rand om data input command (85h). ra ndom data input may be opera t ed multiple time s, reg a rdless of how many time s it is done in a page. the pag e program conf irm comma nd (1 0h) initiates the programming process. writi n g 10h alone wi thout previ o us l y entering the se ri al data wil l not initi a te the pro- g r amming process. the interna l write state controller a u to matically executes the a l gorithms and timings neces s ary for p r ogra m and ve rif y , thereby f r eeing the system control l er for other tasks . on ce the program process starts, the read status register comma nd may be entered to rea d the status register . the system controll er can detect the co mp l e ti on of a program cycle by mon i tori ng the r/b# output, or the status bit (i/ o 6) of the status register. only the read status co mm and a n d res et comm and a r e va lid while program ming is in p r ogre ss. th e write status bit (i/o 0) is valid, when all i n ternal ope r ations are com p l e te (status bit i/o 6 = high). the i n ternal write verify detects onl y errors for "1" s that are not success fully progra mmed to "0"s . the com m and register rema ins in read status comma nd mo d e un til a n o t her va lid co mma nd i s wri tte n to the command re gister. figure 4 0 and figu re 41 detai l s the se quence. 0 fig u re 40. pa ge pro g ra m
rev 0.6 / dec. 2009 47 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 80h address (5 cycle) 11h t dbsy data input a 81h address (5 cycle) 10h t prog data input i/ox r/b# 70h status 1 plane address st 2 plane address nd a i/ox r/b# i/ox r/b# column address 80h address (5 cycle) address (2 cycle) data input 85h data input 70h status 10h prog t figure 41. ra ndom data input 4. 8. m u lti p l ane pr ogr a m dev i ce supp orts multiple plane program. it is possibl e to progra m in pa ralle l 2 page s, one per e a ch pla n e. a mul t iple pl ane program cycle consi s ts of a d o uble ser i a l data loa d ing period in which up to 17 ,28 0 byte s of data may be loade d into the data re gis t er, followed by a no n - v o latile p r og ramming pe rio d where the loaded dat a is program m ed i n to the appropriate cell. th e s erial da ta loadin g pe riod begins by inp u tting the se ria l da ta input command (80h ) , f o l l o w e d b y t h e five cycle add r ess inputs a n d the n serial data for the 1s t pa ge. ad dress f o r this pa ge m u st be wi thin first pl ane (a<22>=0). the data of first page other than those to be prog ramme d d o not need to be load ed. the dev i ce s u pports random d a ta input exactly lik e page prog ram opera t ion. th e dummy p a ge p r og ram confirm comma nd (11h) stops 1st pa ge data input a n d the device becomes b u sy f o r a s h ort time (t db sy ) . o n c e i t h a s b e c o m e r e a d y a g a i n , 8 1 h c o m m a n d m u s t b e i s s u e d , f o l l o w e d b y second page a ddress (5 cycles) a n d its se ria l data inp u t. ad dr ess for this p a ge must be within second plane (a<22 > =1 ). the data of second page other tha n those to be program med do not need to b e loaded . progra m conf irm command (10 h ) ma kes para llel progra mming of both pa ges s t art. user ca n check oper ation status by r/b# pin o r rea d sta t us r egister co mma nd, as i f i t w e r e a n o r m a l p a g e p r o g r a m ; s t a t u s r e g i s t e r c o m m a n d i s a l s o a v a i l a b l e d u r i n g d u m m y b u s y t i m e ( t db sy ) . i n c a s e o f f a i l in first plane or second plane pag e progra m, f a i l b i t o f s t a t u s r e g i s t e r w i l l b e s e t : p a s s / f a i l s t a t u s o f e a c h p l a n e c a n b e c h e cked by multi plane read sta t us. figure 42 deta ils the se quence. figure 4 2 . multi plane pag e program not e s: 1. plan e 0 a n d plane 1 sh ou ld be se le cte d with in the same chip 2. only on e block shou ld b e selected from the each plan e. 3. se le cte d pa ge a ddress except f o r a 22 within two block s mu st be sa me. 4. any comman d betwee n 11h an d 81h is prohibited e x ce pt 70h /7 8h a n d ffh . 5. read sta t us command ca n be 70h or 7 8h.
rev 0.6 / dec. 2009 48 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 4.9 . cache program (a v a ilable only wit h in a block) ca che pr og r a m is an extens ion of the sta n da r d pag e pr og r a m, wh ich is ex ecute d with 8,6 40 b y tes ca che r e g i s t e r s an d s a me byte s data r e gister . after the seri al data inpu t comm and (8 0h) is loa ded to the comm and re gister , f o ll owed by 5 cy cles of a ddr ess, a f u ll or partial pa ge of da ta is latc he d in t o t h e ca ch e r e g i s t e r , a n d t h en t h e ca ch e wr i t e com m a n d (15h ) is lo aded to the comman d regi ster . after that sequence , the data in the cach e r e gister is tr ansf err e d into the d a ta r e gi s t e r for cel l pr ogr a m m ing. a t thi s time, the devic e r e m a ins in bus y state . afte r a l l d a ta of the cache r e gister is tr ans- f e rre d into the data r e gi ste r , the device goes to the r e ady stat e to load the ne xt data i n to the cache r e gister by iss u ing another cache pr o g r a m co mm and sequ ence (80 h -15h). ther e ar e some re stric t ions for cac h e pr ogr a m oper ation. 1. the cache pr o g r a m co mm and i s av ai la b l e onl y wi th in a b l ock . 2 . use r must giv e a ddr ess and data after 80h comm and. the b u sy time of fi rst sequence e q ual s the time it tak e s to tr ansf er the data of cache r e gist er to the data re gister . cel l p r ogr a mm ing of the d a ta of data r e gister and loa d ing of the next d a ta into the cache r e gister is consequently pr oces sed a s a pip eline method. on the se cond and cascad ing s eque n ce, tr a n sf er f r om t h e ca che r e gister to the da ta r e gister is h e ld o f f until cell pr o gr a mming o f curr ent data re gis t er co nten ts ha s been do ne. r e a d sta t us comma nd (70 h ) ma y be issu ed to fin d ou t when the cache register is r e ady by poll in g t he c a c he - bu sy s t a- tus bit (i / o 6). i n addi tion, the status bi t (i/o 5) can be used to dete rmine when the cell pr ogr a mming of the curr ent d a ta r e g i ste r con t ents is com ple te. p a ss/f a il statu s of only the pr ev ious page (i /o 1 ) is a v ailable upon the re turn to re a d y s t a t e . the la st pa ge of th e tar g et p r ogr a mm in g seq u en ce mus t be pr ogr a mme d with actua l ?p a g e p r ogr a m? comma nd (10h ). i f s i ngle p l a n e cache pr ogr a m begins , single plane seq u ence s h ould b e used until single p l a n e cache pr ogr a m is ended. p a ss/f a il status is a v aila ble in two steps . i / o 1 r e turns with th e status of the pr evious page upon r ea d y or i/o6 status bit changi ng to "1", and later i/o 0 wi th th e status of curren t page u p on true r e ad y (retu r ni ng from in tern a l progr a mming) or i/o 5 status bit ch an gin g to "1". i/o 1 ma y be re ad toge th er whe n i/o 0 is ch eck e d. r e f e r to 2.8 . statu s r e gister coding and figu r e 43 f o r mor e de tails.
rev 0.6 / dec. 2009 49 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 80h address (5 cycle) 15h t cbsyw data input a 80h address (5 cycle) 15h t cbsyw data input b i/ox r/b# 80h address (5 cycle) 10h t prog data input i/ox r/b# 70h status a b i/ox r/b# r/b# pin data cache ready /bysy (i/o6) i/o 1 => i/o 0 => invalid invalid page1 invalid page1 page2 page n-2 invalid invalid invalid page n-1 page n data cache ready /bysy (i/o5) 70h sr out 70h sr out 80h-add-data-15h 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 70h sr out page 1 page 2 page n-1 page n page 1 page 2 page n-1 page n during both i/o6 and i/o5 return to high, the pass/fail for previous page and current page can be shown through i/o1 and i/o0 concurrently. prog t cbsyw t cbsyw t cbsyw t pass / fail status for each page programmed by the cache program operation can be detected by the read status operation. i/o 0 : pass / fail of the current page program operation. i/o 1 : pass / fail of the previous page program operation. the pass / fail status on i/o 0 and i/o 1 are valid under the following conditions. status on i/o 0 : ready / busy is ready state. the ready/ busy is output on i/o 5 by read status operation or r/b pin after the 10h command. status on i/o 1 : data cache ready / busy is ready state. the data cache ready / busy is output on i/o 6 by read status operation or r/b pin after the 15h command. figure 43. cache program
rev 0.6 / dec. 2009 50 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 4. 10. multi plane cache prog ram (available only within a block) the dev i ce sup p orts multi plane cache program, which enab le s high pro gram th ro ugh put by program ming two page s. the ser i a l d a ta-loa ding per i od be gins by inputting the se rial d a ta i n put comm and (80 h ), f o llowe d by the f i v e cycle addr ess inputs and then se ria l da ta for the f i rs t pa ge. addres s for this page must be with in first plane (a<22>=0). the data of first pa ge othe r than those to be programm ed do not need to be loade d . the device s u pports ra ndom d a ta input exactly lik e pa ge progra m oper ation. th e d u mmy pa ge p r og ram conf irm comm and (1 1h) stops 1s t page data input and the de vice becomes busy for a short time (tdbsy). once it ha s be come ready aga i n , 81h comm and must b e is sued , f o llowe d by 2 n d p a ge a ddres s (5 cycles) and its serial da ta input. addres s for this p a ge m u st be within second plane (a<2 2>=1). the data of second p a ge othe r tha n th ose to b e programm ed do not need to be loade d . cache progra m confirm comma nd (15h) make s par a lle l pr ogra mming of both pa ges sta r t. a n d las t page inputs program con f irm comma nd (10h ). the la st pa ge of th e tar g et p r og r a mm ing seq u ence mus t be pr ogr a mme d with actua l p a ge pr ogr a m command (10h). if the oper atio n is term in ated, i ssue ffh r e se t bef o re next o per atio n. if m u ltiplan e cache program begins, m u ltiplane seq u ence should b e us ed un til mu ltiplane cache pr og r a m is end e d. fig u re 4 4 shows the command seq u en ce for multi plane cache program operation. after the "15h"or"10h" com m and , the res u lt per pla n e of the opera t ion is s h own thr o u gh th e "78h " mu lti p l a n e re ad s t atu s com m an d. figur e 4 4 . mult i pl ane cache pr ogr a m no tes : 1. pl a n e 0 and plan e 1 sh ould be s e le cted with in the same chip 2. only on e block sh ou ld be se lecte d f r om the e a ch p l ane . 3. multi p l a n e ca che p r ogr a m is a v ailable only within a block per p l ane . 4 . selected p a ge ad dr ess ex cept f o r a22 within two block s mu st be s a me. 5. the oper ation h a s to be te rminate d with ?1 0h? comma nd. ? 6. an y comma nd b e tween 11h and 81h is pr oh ibited ex cept 70 h/78h and ffh. 7 . r e ad statu s comman d can be 7 0 h or 78 h. r e ading th e status per p l ane is a v a i lable only 78h . 80h t cbsyw a 80h 81h i/ox r/b# a address (5 cycle) data input 11 h address (5 cycle) data input 11 h 81h address (5 cycle) data input 15h t dbsy address (5 cycle) data input 10h 78h address (3 cycle) status per plane column address : v alid page address : page m plane address : fixed low block address : block j column address : v alid page address : page m plane address : fixed high block address : block k column address : v alid page address : page m+n plane address : fixed low block address : block j column address : v alid page address : page m+n plane address : fixed high block address : block k i/ox r/b# t prog t dbsy
rev 0.6 / dec. 2009 51 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 4.11. copy-bac k program copy -back pr ogr a m with r e ad f o r copy -back is configur ed to q u ickly a n d e f ficiently r e write da ta stor ed in one page wi thout data r e loadi n g whe n the bi t e r r o r is not i n data store d . since the time-consu mi ng re-l oa di ng cycles a r e r emo v e d, the sys t e m perf ormance is impr o v e d . the be nef i t is especially obvious when a p o rtion of a block is upda ted and the r e st of the bl ock needs to be co p i ed to the ne wly assigned f r ee b l ock. copy -back ope r a t ion is a sequential ex e- cu tion of r e ad f o r co py -b ack an d o f co py -back pro g r a m w i th th e des t in ation pag e add r e ss. a r e ad ope r a t ion with "35h " comman d an d th e ad dr ess of the sou r ce pag e mo v e s th e whole 8,640-by te da ta into th e intern al da ta bu f f er . a bit er ror i s checke d by sequenti al r e ading the data output. i n the case wher e ther e is no bit err o r , the data do not need to be r e loa d ed. ther ef or e, cop y -back pr o g r a m oper atio n is ini t iated by issu in g p a ge- c opy da ta - i n p ut comma nd (8 5 h ) with destina t ion page addr es s. a c tual pr ogr a mming ope r a t ion begins after pr o g r a m co nfirm command (10h) is issued. once the p r ogr a m pr ocess starts , the r e ad status r e gister com m and (70h) ma y be enter e d to re ad the statu s re gister . the s y stem controller can detect the completion of a prog ra m cycl e by moni toring the r/b# output, or the status bit (i/o 6 ) of the status register. when the copy-ba c k progra m is complete, the write status bi t (i/o 0) may be checked. the comma nd re gis t er rema ins in re ad status com mand mo de until anothe r valid command is written to the com - ma nd re gis t er. dur i ng copy-back program, da ta modificati on is possible us ing random data input comm and (8 5h) as sh own in figure 45. f i g u re 45. copyback program 00h address (5 cycle) 35h data output t r 85h address (5 cycle) data t prog i/ox r/b# target address 85h address (2 cycle) data 10h 70h status column address 1,2 i/ox r/b# source address a a
rev 0.6 / dec. 2009 52 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : v alid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : v alid page address : page n plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data 11h i/ox r/b# d column address 1,2 : valid 81h address (5 cycle) data 10h data 85h address (2 cycle) 85h data t prog i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) 05h e0h data output column address : v alid page address : page n plane address : fixed high block address : block q t dbsy 4. 12. mul t i pl ane copy-back program mu lti plan e copy-back program is an exte nsion of copy -back progra m, for a sin g le plane with 8,640 by te pa ge reg i s t ers. since the de vice is equipp ed with two me mory planes, acti vating the two sets of 8 , 64 0-byte page reg i ste r s e n ab les a si- mu ltaneou s programmin g of two pages. figure 46 a n d figure 47 show comma nd se quence for the multi plane copy-back op eration. f i rst case, fi gure 46, shows random data i n put of two plane s that s t arted right after fi nishing random data out- put of pre v ious two planes. se cond case, fig u re 47 , shows th e random data input of each pl ane whi ch started right afte r finishi n g the random data output of e a ch plane . figur e 4 6 . mult i pl ane copyback pr ogr a m
rev 0.6 / dec. 2009 53 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : v alid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : v alid page address : page m plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data data i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) i/ox r/b# d column address : v alid page address : page m plane address : fixed high block address : block q column address 1,2 : valid 81h address (5 cycle) data 10h e0h 05h address (2 cycle) 85h data t prog 85h 11h t dbsy data output figure 47. multi plane copyback program 4.13. block erase t h e erase ope r ation is done on a block ba sis . block add r ess lo ading i s accompli shed in tw o cycles i n i t iated by an erase setup comm and (60 h ). only addre ss a22 to a32 is v a lid whil e a 14 to a21 is ignored. th e eras e con f irm comman d (d0h ) fo llo wing the bloc k address lo ading i n i t ia t e s the inte rnal erasing process . this two-step sequence of setup followed by e x e c ution com man d ens u res that m emory conten ts ar e not accidentally era s ed due to external noise conditio ns. at the risi ng edge of we# afte r the er as e confirm com m and input, the internal wr ite controlle r handle s erase a n d era s e verif y . once the erase process sta rts, the rea d status register comm and ma y be e n tere d to r e ad the sta t us register. the sy stem controll er can detect the c o mpletion o f an e r ase by monitori ng the r/ b# output, or the status bi t (i / o 6) of the status re gi s t er. only the read status command and reset com m and ar e vali d while erasing is in progres s. when the e r ase op - eratio n is co mpl e ted, the write status bi t ( i /o 0) ma y be check e d. figure 48 details the sequence .
rev 0.6 / dec. 2009 54 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 60h 70h address (3 cycle) d0h status t bers i/ox r/b# row add 1,2,3 60h 70h address (3 cycle) 60h status t bers address (3 cycle) d0h page address : fixed low plane address : fixed low block address : block n i/ox r/b# page address : fixed low plane address : fixed high block address : block m figure 48. block era s e 4.14. mul t i plane bl ock erase. multiple p l a n e e r ase, allows para llel era s e of two blocks, one per each memory p l a n e. block e r ase s e tup comma nd (60h) mu st be repe ated two tim e s, each time f o llowed by first block and second b l ock a d - dres s respectiv e ly (3 cy cle s each). as for block erase , d 0 h command mak e s emb e dded opera t ion s t art. multi plane e r ase do es no t nee d any dum m y b u sy time betwee n first an d seco nd block addre ss insertion. a ddr ess limitation required for mu l t ipl e pl ane pr o g r a m ap pli e s al so t o mul t i p l e pl an e er a s e, as w e ll a s o p er a t io n pr og r e ss c a n b e c h e c ked like fo r m u l t ip le plane prog ram. refe r to the de tail s e que n ce a s shown below. figure 49. multi p l a n e block erase 4.15. reset the de vice of fers a res e t fea t ure, executed by writing ffh to the comma nd re gis t er. when t h e dev i c e is in b u sy st at e duri ng random r e ad, program or erase mode, the rese t oper ation will a b ort these opera t ions. the contents of memory cells being a l tered a r e no longer v a lid, a s the data will be pa rtia lly programm ed or eras ed. the command register is cleared to wait for the ne x t comm and, an d th e statu s register is cle a red to v a lue e0h wh en wp# is h i g h . refe r to 2.8. sta t us register coding for device status a f ter res e t opera t io n. if the device is alrea d y in r e set state, the com m and re g- ister will not accept a new reset command. the r/b# pin go es low for t rs t after the re set command is w r itten. refer to fi gure 50.
rev 0.6 / dec. 2009 55 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash i/ox r/b# ffh rst t figure 50. reset
rev 0.6 / dec. 2009 56 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash data out 00h status row . add3 78h row . add2 row . add1 00h 30h 00h 30h address (5cycle) address (5cycle) 00h status row . add3 78h row . add2 row . add1 data out chip 2 chip 1 chip 1 chip 1 chip 2 chip 2 i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) 5. interleaved op eration interlea ving operations improve the s y stem throughput comp ared to no n- in terl ea v i n g oper a t ions. in the stacke d d e vice shar in g a common ce# p i n , inte rle a ve d operation is av ailable. wh e n b o t h ch ip are re ad y s t ate , i n p u t a co mm a n d to the c h ip #1 . a n d th en , wh il e ch ip #1 is b u s y sta t e , is s u e a com m a n d to the oth e r ch ip . wh e n p e r f or m i n g in ter l ea v e d op e r a - t i ons, the ope r ations shall be the sa me type. the functi ons that m a y be used i n t h e in t e r l ea v e d o p er a t io ns a r e p a ge r e a d , pag e pro g ram , blo c k era s e, mu lti plan e pa ge read, mu lti p l a n e p a ge p r ogr a m, and m u lti p l ane block erase . du ring inter- lea ved ope r at i o n s , 70h c o mm and is pr oh i b it ed exceptionally. each c h ip status ca n be checked by multi plane read sta t us c o m m a n d ( 7 8 h ). t h e r / b # p i n s h o w s w h e n b o t h c h ip a r e r e a d y o r bu s y . w h i l e e i t h e r c h i p is b u s y , r / b # p i n i s lo w . a l l c h ip s a r e re ad y s t a t e an d in te rle a v e d op e r ati on s are co mp l e te , r/b# p i n g o e s high. c a che f unction and copy back f u nc- tion a r e impossible for interl eaved o p eration. 5.1. interleave d pag e read f i gure 51 shows how to perform inte rl e a ve d page rea d operat ions. in figure, the s t atus register is monitored f o r oper- ation com p l e ti on with the mu lti plane status read ( 7 8h) command. when the host ha s issued page re ad comma nds to multi p l e die at the sam e time, the host sha l l iss u e mu lti plane sta t us read (78h ) com m an d be fore reading da ta from eith er d i e. t h i s e n su r e s t h at on ly t h e d i e s e le cted by the 78h command re sponds to a da ta output cycle after being put i n data output mode with a 00h command, and th us av oiding bus co nten tio n . the h o st can u s e 7 8h com m and s to re ad ou t da ta from an oth e r die. figure 51. interl eaved page read not e : 70h command is p r oh ib ite d durin g interleav e d opera t ion s .
rev 0.6 / dec. 2009 57 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash r/b# (chip 1 internal) i/ox 80h address (5cycle) data input 10h 80h address (5cycle) data input 10h row add.1 row add.2 row add.3 status 80h address (5cycle) data input 10h chip 1 chip 2 chip 1 chip 1 r/b# (chip 2 internal) r/b# (external) 78h a 00h address (5cycle) 78h row add.1 row add.2 row add.3 status 05h address (2cycle) e0h chip 2 05h address (2cycle) e0h 00h address (5cycle) data output chip 2. plane 0 chip 2. plane 0 chip 2. plane 1 data output 00h address (5cycle) 05h address (2cycle) e0h data output chip 1. plane 0 chip 1. plane 0 chip 2. plane 1 a 60h 60h 60h 60h 30h 78h 00h 05h e0h address (3cycle) address (5cycle) 30h address (3cycle) address (3cycle) row add.1 row add.2 row add.3 status address (5cycle) address (2cycle) data output chip 1 chip 1 chip 2 chip 2 chip 1 chip 1, plane 0 chip 1, plane 0 chip 1, plane 0 i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) 5.2. interleaved multi plane page read fi g u re 52 shows how to p e rform interleave d multi p l a n e pa ge rea d oper ations using the multi plane re ad status (7 8h) com m and to monitor the status register for operati o n comp letio n . when the ho st has i ssued multi pla n e pa ge rea d co mmands to multiple di e at the sa me time, the hos t shall issue multi p l a n e read s t atus (78h) com m and b e fore reading data from e i ther die. this ensur e s that only the d i e selected by the 7 8 h comma nd responds to a data output cycl e aft e r being p u t in da ta output mo d e with a 00 h command and 5 a ddress cy cles, and thus avoiding bu s contention. the in- terleav ed multi pla n e page read oper ation mu s t meet two-p l a n e a ddress i ng requirements. figure 52. interle a ved multi p l a n e pa ge read no te: 70h com m and is prohibited du ri ng interleaved ope r ations. 5.3. interleaved page program fig u re 5 3 sh ow h o w to perf orm in terleav e d p r ogram p age opera t ions . ran d om data inp u t (8 5h) is per m itte d during interleaved program page operati o ns . figure 53. interle a ved page program no te: 70h com m and is prohibited du ri ng interleaved ope r ations.
rev 0.6 / dec. 2009 58 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash r/b# (chip 1 internal) i/ox r/b# (chip 2 internal) r/b# (external) r/b# (chip 1 internal) i/ox r/b# (chip 2 internal) r/b# (external) a a row . add.1 row . add.2 row . add.3 78h 80h status address. (5cycle) data input 11h 81h address. (5cycle) data input 10h 80h address. (5cycle) data input 11h 81h address. (5cycle) data input 10h 80h address. (5cycle) data input 11h 81h address. (5cycle) data input 10h chip 1 chip 1 chip 2 chip 2 chip 1 chip 1 chip 1 r/b# (chip 1 internal) i/ox 60h chip 1 chip 2 chip 1 r/b# (chip 2 internal) r/b# (external) address (3cycle) d0h 60h address (3cycle) d0h 60h address (3cycle) d0h 60h address (3cycle) d0h chip 2 5.4. in te rle ave d multi plane page program figure 54 shows how to perform interl ea ved m u lti plane page pro gram o pera t ion s . t h e inte rle a ve d two- plan e p r o- gra m page opera t ion must meet two-plan e a ddres sing require m ents . random d a ta input (85h) is pe rmitted during in- te rle a ved multi plane pa ge progra m operation. figure 54. interleaved multi plane page program note: 7 0 h co mma nd is pr oh ibited during in terleav e d o p era t io ns . 5.5. in te rle ave d block eras e figu re 55 shows how to perf orm in terlea ved blo c k era s e o p era t io n. figure 55. inter l eaved block erase note: 7 0 h co mma nd is pr oh ibited during in terleav e d o p era t io ns .
rev 0.6 / dec. 2009 59 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash r/b# (chip 1 internal) i/ox 60h chip 1 chip 1 chip 2 r/b# (chip 2 internal) r/b# (external) address (3cycle) 60h address (3cycle) d0h chip 2 60h address (3cycle) 60h address (3cycle) d0h 78h row . add 1. 60h address (3cycle) 60h address (3cycle) d0h row . add 2. row . add. 3 status chip 1 chip 1 chip 1 5.6. in te rle ave d multi plane block erase figure 56 shows how to perform two type s of inter l eaved mu lti pla n e block eras e ope r atio ns. this o p eratio n must meet two-p l a n e a ddres sing req u irements. figure 56. interleaved multi p l ane block erase note: 70h command is prohibited during interleaved operations.
rev 0.6 / dec. 2009 60 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 3v device = 2.7v t cs ffh 2.7v 1 (max) ms 10 (max) 50 (min) 2 (max) ms vcc ramp starts : dont care : undefined vcc 0v ce# wp# cle we# ale re# i/ox r/b# 6. other features 6.1. data pr otection & p o wer on/off s e quence the device is des i gned to of fer protection fr om an y in volu ntar y p r ogr a m/eras e du ring powe r-tra n sitions. an internal v o ltage de- tector disa ble s all f unctions whene v er v cc is below about 2 . 0v (3.3v dev i ce). wp# pi n provides h a rdware protecti on and is rec - ommended to be kept a t vi l du ring power-up a n d p o wer-down. the rese t command (ffh) mus t be issued to all di e s as the first com m and a f ter dev i ce is powe r up. each r/b# will be busy for ma ximu m of 2m s af ter rese t comm and is is sued . in this time, the accepta ble com m an d is 70h or 78h. 0 figure 57. data protection and power on / off
rev 0.6 / dec. 2009 61 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash rp v a lue guidence rp (min) = = where il is the sum of the input current of all devices tied to the r/b# pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3v , t a = 25c, c l =50pf fig. rp vs tr , tf & rp vs ibusy vcc (max. ) - v ol (max. ) 3.2v p$?, l i ol + ?, l rp ibusy rp (ohm) ibusy ibusy [a] tr , tf [s] tf 3.3 381 290 1.65 96 189 1.1 0.825 4 .2 4 .2 4 .2 4 .2 busy r eady vcc v oh tr tf v ol v ol : 0.4v , v oh : 2.4v vcc 300n 3m 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b# 6.2. ready / busy t h e dev i ce has a ready / bu sy ou tput th at p r ov id es me thod of in di cati ng the completion of a page progra m, eras e, cop y - back and r a n d om r e ad c o m p le tion . t h e r / b# p i n i s nor m a l ly h i g h an d g o e s to low whe n th e de v i ce is b u s y ( a f t e r a r e se t, r e ad , pr o g ra m , a n d eras e ope r ation). it re turns to high wh en the interna l contro ller ha s finishe d the oper ation. the pin is a n open -drain driv er thereby all o wing two or m o re r/b# outputs to be or-tied. becaus e pul l -up resi stor value is relate d to tr (r/b #) and curre n t dra in during busy (ibusy), an a ppropriate value can be obtaine d with the fol l owi n g re ferenc e chart (figur e 58 ). its value can be de- t e r m in ed by t h e fo ll o w in g gu ida n c e . 0 figure 58. ready / busy
rev 0.6 / dec. 2009 62 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 80h 10h we# i/ox wp# r/b# ww t 80h 10h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 6.3. write protect operation the eras e a n d progr a m opera t ions a r e automatically rese t wh en wp# goes low (tww = 100ns, min). the op erations are enabled a n d d i s a bled a s follows (fig ure 5 9 ~ 62). figure 59. enable pr ogr a mmi ng figure 62. disable erasing figure 60. dis a ble programming figu re 61. en able er asi n g
rev 0.6 / dec. 2009 63 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 7. application notes and comments 7.1. paired page address information paired page address paired page address 04 1 5 28 3 9 6c 7 d a1 0 b 1 1 e1 4 f 1 5 12 1 8 13 19 16 1c 17 1d 1a 2 0 1b 21 1e 2 4 1f 25 22 2 8 23 29 26 2c 27 2d 2a 3 0 2b 31 2e 3 4 2f 35 32 3 8 33 39 36 3c 37 3d 3a 4 0 3b 41 3e 4 4 3f 45 42 4 8 43 49 46 4c 47 4d 4a 5 0 4b 51 4e 5 4 4f 55 52 5 8 53 59 56 5c 57 5d 5a 6 0 5b 61 5e 6 4 5f 65 62 6 8 63 69 66 6c 67 6d 6a 7 0 6b 71 6e 7 4 6f 75 72 7 8 73 79 76 7c 77 7d 7a 8 0 7b 81 7e 8 4 7f 85 82 8 8 83 89 86 8c 87 8d 8a 9 0 8b 91 8e 9 4 8f 95 92 9 8 93 99
rev 0.6 / dec. 2009 64 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 9 6 9c 97 9 d 9a a0 9b a 1 9e a4 9 f a 5 a2 a8 a3 a 9 a6 a c a7 ad aa b0 ab b1 ae b4 a f b5 b2 b8 b 3 b 9 b 6 bc b7 b d ba c0 bb c1 be c4 bf c5 c2 c8 c3 c9 c6 cc c7 cd ca d0 cb d1 ce d4 cf d5 d 2 d8 d3 d9 d 6 dc d7 dd da e0 db e1 de e4 df e5 e2 e8 e3 e9 e6 e c e7 ed ea f0 eb f1 ee f4 ef f5 f2 f8 f3 f9 f6 f c f7 fd fa fe fb ff w h e n p r og ram op e r ati o n is ab n o rm al ly a b o r te d (e x. p o we r-d o wn, reset), not only page da ta unde r progra m b u t also a couple d row p a ired page data ma y be dama ged. for e x a mpl e, during pag e p r og ram op eration of pag e a ddress 05 h is aborted by rese t or power down , th e da ta of 00 h, 01h , 0 4h, an d 05h pag e add r ess m a y b e spoile d.
rev 0.6 / dec. 2009 65 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 7.2. ex tra block description dev i ce in clu d es extra f e atu r es lik e us er otp, uniq ue id a n d rea d id2. us er otp, unique i d can be p r ogr a mmed only once a n d ca nnot b e era s ed. the user otp use d one b l ock w h ic h locates the se cond bloc k of p l a n e 0 (addres s<32:22 > = 0002h ). unique i d block has 6 4 page s, locates th e first block of p l a n e 0 an d the f i r s t 64 pag e s of the block (a d- dress < 32:22> = 0 000h , add r ess<21 :14> = 00h ~ 3fh ) . re ad id2 can be only rea d, the siz e is on e page . ph ysically, readi d 2 area exists in plane1, but use r block a ddres s does not care internally. to exi t extra f e atu res, 07 h or ffh com- ma nd ca n be used. 7.3. acceptable command after 80h after program start com m and (80h) is in putte d , do not inpu t an y comman d except 85h , 10h , 11 h, 1 5h, and ffh . if a com mand is inputte d except these comma nds , the program op eration cannot be e x e c uted. 7.4. acceptable command betwee n start comman d an d confirm command only reset com m an d is ava i la ble betwe e n start com m and s a n d confirm comm ands se t (start com mand-a ddress - conf irm com mand style ) that is mentione d in 1.7 comma nd set. if ot h e r comma nd is inpu tted, the opera t io n ca nn ot be executed. do not inpu t any comm and s except ffh. for in stan ce, it is im possible to p e rform a n o r m al pa ge read ope r ation , if a n y com m and is in putte d between pa ge rea d comman d set (00h - 5 addr ess cy cle - 30 h). 7. 5. re str i c t io n of rea d s t atus va lue in m u lti p l ane opera t io n du rin g m u lti pla n e ope r ation , on ly 70h , 7 8 h, an d ffh are a v a i lable between 11h-81 h . but, the pass/fail output info rmatio n o f 7 0 h a n d 7 8 h i s n o t v a l i d . d u r i n g t h i s t i m e , o n l y r e a d y / b u s y ( i / o 6 a n d i / o 5 ) s t a t e c a n b e c h e c k e d . r e f e r t o f i g u r e 6 3 .
rev 0.6 / dec. 2009 66 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash 80h i/ox r/b# address data i/o6 => i/o5 => i/o1 => i/o0 => valid invalid invalid invalid 11h 70h sr out 81h address data 10h 70h sr out v alid invalid invalid invalid v alid invalid invalid v alid 70h sr out t prog t dbsy io 0 = 0, pass io 0 = 1, fail figure 6 3 . re strictio n read st at us in mult i plane operation 7 . 6. page program failure if the p a ge pr ogra m opera t ion for pa ge a ddres s n is fail, rema in data in data register may be dif f ere n t to inp u t da ta b y host. the refore, do not attempt to program the page addre ss n i n an oth e r bl o c k w i th ou t the data input seque n ce. the same input sequence of 80h comma nd, ad dress and data is neces s ary . 7.7. restriction multi plane operation to p r event a b normal multi plane opera t io n, do not inp u t b a d block add r ess to al l mult i plane operatio n. otherwise, the input data of valid block could be lost a n d the operation could be abnorm ally stopped.
rev 0.6 / dec. 2009 67 preliminary H27UBG8T2A series 32gb (4096m x 8bit) nand flash k o h 2 7 u b g 8 t 2 a x x- x r x y w w x x - hynix - kor - H27UBG8T2Axx-xx h : hynix 27 : nand flash u : power supply bg : density 8 : bit organiztion t : classification 2 : mode a : v ersion x : package t ype x : package material : hynix symbol : origin country : part number : u (2.7 v~ 3.6 v) : 32 gibit : 8 (x8) : multi level cell + single die + large block : 2(1nce & 1r/nb; sequential row read disable) : 2nd generation : t(48-tsop1), y(52-lga) : blank(normal), r(lead & halogen free) x : bad block x : operating t emperature : b(included bad block), s(1~5 bad block), p(all good block) : c(0 e ~70 e ), i (-40 e ~85 ep - y : y ear (ex: 9 = year 2009, 0 = year 2010) - ww : w ork w eek (ex:12 = work week 12) - xx : process code note - capital letter - small letter : fixed item : non-fixed item marking information - vlga/tsop1

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